1. Field of the Invention
The present invention relates to an operation device used in an information processing device for evaluating logical expression and particularly relates to a logical expression evaluation device which makes logical expression evaluation with treating a logical expression comprising logical unit elements "0" and "1", OR operator and symbols for operation level specification "(" and ")" as vector data. The present invention also relates to a vector processing device used in a large scale information processing device adopting the vector operation method.
2. Description of the Prior Art
In a conventional particle model using atomic code, in general, a particle usually moves or remains in a complicatedly shaped space with inclusion relations of zones or cells combining basic shapes (primitives) such as spheres, cylinders, rectangular parallelepipeds and circular cones. Zones are numbered in advance and the particles in a certain zone have the number of that zone as their attribute.
When a particle moves in a space, the zone number of the particle can sometimes differ from the number of the zone where the particle is currently located. Such discrepancy may be possibly caused by contradiction in shapes defined by input data, accumulated errors arising in crossing calculation for particle paths and zone boundaries as well as logical error in programming the applicable code. Such particles causing discrepancy are referred to as lost particles, which are not to be subjected to calculation.
The MCNP code checks consistency every time a particle enters a new zone to find out lost particles.
A zone in MCNP code is defined by listed combinations of surrounding planes. Such a list expression is generated by an input processing routine using the input data. Whether a particle is in the correct zone or not is judged by checking that the positive and negative directions of the planes surrounding the particle have the same meaning as those in the input data. If they have the same meaning, the plane number in the input data is replaced with "1", and if not, it is replaced with "0" so that a zone list as above is prepared.
Such a zone list expression is evaluated as a logical expression according to the priority for Boolean operator and the obtained value is referred to as LGEVAL. If the LGEVAL value is "0", it means that the particle is in an inconsistent zone, or it is a lost particle.
The MCNP method is considered effective in finding input data error and preventing a program from running in an unexpected way during code development.
In conventional practices, logical expression evaluation as described above is processed by software. Besides, since a program for such evaluation has a structure with frequent conditional decisions and branching steps, scalar processing is usually used.
Thus, a logical expression is conventionally evaluated by scalar processing on software. Since it requires some hundreds of machine cycles to process even a single component in a logical expression, it takes long to evaluate an entire logical expression. This is a significant drawback which obstructs higher speed processing of atomic code for a particle model as described above.
On the other hand, a conventional vector operation device gives processing as shown below. Supposing an example where the behavior of a plurality of particles is simulated using Monte Carlo code (MCNP code), there may be many steps for particle classification processing using a program as shown in FIG. 8. Such a program is described in FORTRAN. This processing is to classify data A(I) to the array B and the array C depending on whether the array M(I) has a positive value or not for I values from 1 to N. Such particle classification was processed by mask and compress operations in a conventional vector processing device.
Referring to FIGS. 9 and 10, the flow of such processing is described below. FIGS. 9 and 10 are flowcharts to illustrate the conventional processing.
Mask generation 901
A logical expression M(I).GT.O as shown in FIG. 8 is evaluated with vector operation. The evaluation result ("1" for true and "0" for false) is stored in the mask register for every loop.
Compress (1) 902
Data A(I) on the input vector register 1 is checked to compress those having "1" at the corresponding location on the mask register so that they are stored in the output vector register (2). At the same time, the number of "1"s on the mask register determined by component number counting instruction is stored to the register. Then, this register value and J1INIT are summed and the result is stored at J1 memory location.
Storing (1) 903
The compressed data on the vector register are vector stored with using the above register value as the vector length and the memory address of B (J1INIT+1) as the initial memory location.
Mask reversing 904
All components on the above mask register are reversed ("1" is changed to "0", and "0" is changed to "1").
Compress (2) 905
Data A(I) on the input vector register 1 is checked to compress those having "1" at the corresponding location on the mask register and store them in the output vector register 2. The number of "1"s on the mask register determined by component number counting instruction is stored to the register. Then, this register value and J2INIT are summed and the result is stored at J2 memory location.
Storing (2) 906
The data on the vector register compressed in the compress process 2 are vector stored with using the register value obtained in the compress process 2 as the vector length and the memory address of C (J2INIT+1) as the initial memory location. However, if the vector length N excesses the maximum length that can be processed with vector operation, it is required to divide the data into a plurality of pieces so as to allow a procedure having a length below the maximum loop length to be repeated.
Thus, conventional vector processing as described above requires a mask reversing step, two compress steps and two component number counting steps. Such inefficient vector processing is a drawback. Such inefficiency is a drawback obstructing higher speed processing.